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CD74HC4059M96

CD74HC4059M96
Mfr. #:
CD74HC4059M96
描述:
Counter ICs Prog Div by N
生命周期:
制造商新产品。
数据表:
CD74HC4059M96 数据表
交货:
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CD74HC4059M96 更多信息 CD74HC4059M96 Product Details
产品属性
属性值
制造商：
德州仪器
产品分类：
计数器 IC
RoHS：
Y
安装方式：
贴片/贴片
包装/案例：
SOIC-24
逻辑系列：
慧聪
位数：
1 bit
计数顺序：
向下
工作电源电压：
2 V to 6 V
最低工作温度：
- 55 C
最高工作温度：
+ 125 C
系列：
CD74HC4059
打包：
卷轴
功能：
柜台
工作温度范围：
- 55 C to + 125 C
输出电流：
+/- 5.2 mA
品牌：
德州仪器
产品类别：
计数器 IC
出厂包装数量：
2000
子类别：
计数器 IC
单位重量：
0.022025 oz
Tags
CD74HC4059M, CD74HC4059, CD74HC405, CD74HC40, CD74HC4, CD74HC, CD74H, CD74, CD7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    F***z
    F***z
    CL

    Good product

    2019-05-03
    M***S
    M***S
    RU

    Order shipped quickly. In moscow received in 11 days. The track was tracked only to russia. Packed in a puffy envelope. Chips came without damage. I recommend to all this seller.

    2019-03-11
    P***y
    P***y
    BY

    Price&quality ok.

    2019-01-18
    E***a
    E***a
    ES

    all perfect thanks since Spain¡!

    2019-06-25
***as Instruments
High Speed CMOS Logic CMOS Programmable Divide-by-N Counter 24-SOIC -55 to 125
***ical
Counter/Divider Single 5-Bit Decade Down 24-Pin SOIC T/R
***essParts.Net
TEXAS INSTRUMENTS CD74HC4059M96 / IC COUNTER PROG DIV-BY-N 24-SO
***S
IC COUNTER/DIVIDER 5-BIT DECADE DWN SO-24
***as Instruments Inc.
The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs.
***AS INSTRUMENT
The three Mode-Select Inputs Ka,Kb and Kc determine the modulus ("divide-by" number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. For example, in the 10) counters presettable by means of Jam Inputs J5 through J16.
***as Instr.
The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the first counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2).
***TEXAS
The three decades of the intermediate counter can be preset to a binary 15 instead of a binary 9, while their place values are still 1, 10, and 100, multiplied by the number of the 8 mode, the number from which counting down begins can be preset to:      3rd Decade                     1500      2nd Decade                     150      1st Decade                     15      Last Counting Section    1000
***AS INSRUMENT
The total of these numbers (2665) times 8 equals 12,320. The first counting section can be preset to 7. Therefore, 21,327 is the maximum possible count in the 8 mode.
***AS
The highest count of the various modes is shown in the Extended Counter Range column. Control inputs Kb and Kc can be used to initiate and lock the counter in the "master preset" state. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kb and Kc both remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected.
***TEXAS
The counter should always be put in the master preset mode before the 5 mode is selected. Whenever the master preset mode is used, control signals Kb = "low" and Kc = "low" must be applied for at least 3 full clock pulses.
***as Instr.
After Preset Mode inputs have been changed to one of the 8 mode). If the Master Preset mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. If the Master Preset Mode is not used, the counter jumps back to the "Jam" count when the output pulse appears.
***NS
A "high" on the Latch Enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to "low". If the Latch Enable is "low", the output pulse will remain high for only one cycle of the clock-input signal.
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可用性
库存:
Available
订购:
1988
输入数量:
CD74HC4059M96的当前价格仅供参考，如果您想获得最优惠的价格，请提交查询或直接发送电子邮件至我们的销售团队[email protected]
参考价格（美元）
数量
单价
小计金额
1
US$2.71
US$2.71
10
US$2.44
US$24.40
100
US$1.99
US$199.00
250
US$1.87
US$467.50
500
US$1.70
US$850.00
1000
US$1.43
US$1 430.00
由于2021年半导体供不应求，低于2021年之前的正常价格，请发询价确认。
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