CD74AC112E

CD74AC112E
Mfr. #:
CD74AC112E
描述:
Flip Flops Dual
生命周期:
制造商新产品。
数据表:
CD74AC112E 数据表
交货:
DHL FedEx Ups TNT EMS
支付:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
更多信息:
CD74AC112E 更多信息 CD74AC112E Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
人字拖
RoHS:
Y
电路数量:
2
逻辑系列:
交流电
逻辑类型:
JK 负沿触发触发器
极性:
反相/非反相
输入类型:
CMOS、LVTTL
输出类型:
微分
传播延迟时间:
129 ns
高电平输出电流:
- 24 mA
低电平输出电流:
24 mA
电源电压 - 最小值:
1.5 V
电源电压 - 最大值:
5.5 V
最低工作温度:
- 55 C
最高工作温度:
+ 125 C
安装方式:
通孔
包装/案例:
PDIP-16
打包:
管子
功能:
双重的
高度:
4.57 mm
长度:
19.3 mm
工作温度范围:
- 55 C to + 125 C
静态电流:
4 uA
系列:
CD74AC112
宽度:
6.35 mm
品牌:
德州仪器
通道数:
2
输入行数:
2
输出线数:
1
工作电源电压:
1.5 V to 5.5 V
产品类别:
人字拖
重置类型:
设置、重置
出厂包装数量:
25
子类别:
逻辑 IC
单位重量:
0.033570 oz
Tags
CD74AC11, CD74AC1, CD74AC, CD74A, CD74, CD7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    P***c
    P***c
    FR

    Thanks

    2019-02-02
    A***N
    A***N
    RU

    Item serviceable all well but shipping is very long about three months to vroneja

    2019-02-01
    E**a
    E**a
    HR

    Everything ok.

    2019-04-06
    S***v
    S***v
    RU

    The goods did not come!

    2019-06-03
***as Instruments
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and eset 16-PDIP -55 to 125
***ical
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP Tube
***ark
IC, JK-TYPE FLIP FLOP, DUAL, DIP-16
***ASIN
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
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可用性
库存:
Available
订购:
1984
输入数量:
CD74AC112E的当前价格仅供参考,如果您想获得最优惠的价格,请提交查询或直接发送电子邮件至我们的销售团队[email protected]
参考价格(美元)
数量
单价
小计金额
1
US$0.70
US$0.70
10
US$0.58
US$5.80
100
US$0.37
US$37.40
1000
US$0.30
US$300.00
2000
US$0.27
US$544.00
5000
US$0.25
US$1 265.00
10000
US$0.24
US$2 440.00
25000
US$0.23
US$5 850.00
50000
US$0.22
US$11 250.00
由于2021年半导体供不应求,低于2021年之前的正常价格,请发询价确认。
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