SN74S374DWRE4

SN74S374DWRE4
Mfr. #:
SN74S374DWRE4
描述:
Flip Flops Octal D-Ty Positive Edge-Trig F-F
生命周期:
制造商新产品。
数据表:
SN74S374DWRE4 数据表
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更多信息:
SN74S374DWRE4 更多信息 SN74S374DWRE4 Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
人字拖
RoHS:
Y
电路数量:
8
逻辑系列:
74S
逻辑类型:
D型透明锁扣
极性:
同相
输入类型:
平行线
输出类型:
单端
传播延迟时间:
17 ns
高电平输出电流:
- 6.5 mA
低电平输出电流:
20 mA
电源电压 - 最小值:
4.75 V
电源电压 - 最大值:
5.25 V
最低工作温度:
0 C
最高工作温度:
+ 70 C
安装方式:
贴片/贴片
包装/案例:
SOIC-20
打包:
卷轴
功能:
D型总线接口
高度:
2.35 mm
长度:
12.8 mm
宽度:
7.52 mm
品牌:
德州仪器
通道数:
8
输入行数:
3
输出线数:
8
工作电源电压:
4.75 V to 5.25 V
产品类别:
人字拖
出厂包装数量:
1
子类别:
逻辑 IC
单位重量:
0.028254 oz
Tags
SN74S374D, SN74S374, SN74S37, SN74S3, SN74S, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20SOIC
***as Instruments
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up. The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
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OMO.#: OMO-SN74S37N--1190

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可用性
库存:
Available
订购:
3500
输入数量:
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