DC1763A-A

Mfr. #:: DC1763A-A
制造商:: Analog Devices Inc.
描述:: Data Conversion IC Development Tools LTC2195: 16-bit 125Msps ADC, Serial LVDS
生命周期:: 制造商新产品。
数据表:: DC1763A-A 数据表
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产品属性
属性值

制造商：: 模拟设备公司

产品分类：: 数据转换IC开发工具

RoHS：: Y

产品：: 演示板

类型：: 模数转换器

工具用于评估：: LTC2195

工作电源电压：: 3 V to 6 V

系列：: LTC2195

品牌：: 模拟设备公司

产品类别：: 数据转换IC开发工具

出厂包装数量：: 1

子类别：: 开发工具

Tags: DC1763, DC176, DC17, DC1

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

DC1763A-A 描述

***va Crawler: LTC2195: 16-bit 125Msps ADC, Serial LVDS Outputs, 5-170MHz, req DC1371 and DC1075

***ark: 16Bit Analog To Digital-Adc Evaluation Board, Requires Dc718 Or Dc590

***ical: LTC2195 ADC Demonstration Circuit 125MSPS Pscope IDE

***ment14 APAC: 16BIT ADC Eval Brd, Rq. DC718 or DC590

***log Devices: The LTC2195/LTC2194/LTC2193 are 2-channel, simultaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 76.8dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.4LSBRMS. To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs two bits or four bits at a time. At lower sampling rates there is a one bit per channel option. The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Applications Communications Cellular Base Stations Software-Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing

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