DC750A-C

Mfr. #:: DC750A-C
制造商:: Analog Devices Inc.
描述:: Data Conversion IC Development Tools LTC2230CUP - High Speed ADC, VCC = +3.3V
生命周期:: 制造商新产品。
数据表:: DC750A-C 数据表
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更多信息:: DC750A-C 更多信息 DC750A-C Product Details

产品属性
属性值

制造商：: 模拟设备公司

产品分类：: 数据转换IC开发工具

RoHS：: Y

产品：: 演示板

类型：: 模数转换器

工具用于评估：: LTC2230

工作电源电压：: 3.1 V to 3.5 V

系列：: LTC2230

品牌：: 模拟设备公司

产品类别：: 数据转换IC开发工具

出厂包装数量：: 1

子类别：: 开发工具

Tags: DC750, DC75, DC7

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

DC750A-C 描述

*** Electronic Components: Data Conversion IC Development Tools LTC2230CUP - High Speed ADC, VCC = +3.3V

***va Crawler: LTC2230CUP | High Speed ADC, VCC = +3.3V, 170Msps, 10-Bit 1MHz < AIN < 100MHz (Requires DC890 and LVDS_TRANSFORMER)

***ical: LTC2230CUP High Speed ADC Demonstration Circuit

***ponent Distributors Inc.: LTC2230 Evaluation Kit(Fin= 1-100MHz)

***log Devices: The LTC2230 and LTC2231 are 170Msps/135Msps, sampling 10-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2230/LTC2231 are perfect for demanding communications applications with AC performance that includes 61dB SNR and 75dB spurious free dynamic range for signals up to 200MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.12LSBRMS. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Applications Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment

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