SN74ALVC7814-40DLR

Mfr. #:: SN74ALVC7814-40DLR
描述:: FIFO 64 x 18 3.3-V ASynch FIFO Memory
生命周期:: 制造商新产品。
数据表:: SN74ALVC7814-40DLR 数据表
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更多信息:: SN74ALVC7814-40DLR 更多信息 SN74ALVC7814-40DLR Product Details

产品属性
属性值

制造商：: 德州仪器

产品分类：: 先进先出

RoHS：: Y

包装/案例：: SSOP-56

打包：: 卷轴

品牌：: 德州仪器

安装方式：: 贴片/贴片

工作电源电压：: 3 V to 3.6 V

产品类别：: 先进先出

出厂包装数量：: 1

子类别：: 内存和数据存储

单位重量：: 0.024508 oz

Tags: SN74ALVC7814, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ALVC7814-40DLR 描述

***et: FIFO Mem Async Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R

***i-Key: IC MEMORY FIFO 64X18 56-SSOP

***as Instruments: A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7814 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. These memories are designed for 3-V to 3.6-V VCC operation. Data is written into memory on a low-to-high transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 64. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect. Status of the FIFO memory is monitored by the full (FULL\), empty (EMPTY\), half-full (HF), and almost- full/almost-empty (AF/AE) flags. The FULL\ output is low when the memory is full and high when the memory is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 32 or more words and low when it contains 31 or fewer words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN\) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (64 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (63 - Y) words. A low level on the reset (RESET\) resets the internal stack pointers and sets FULL\ high, AF/AE high, HF low, and EMPTY\ low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up. The first word loaded into empty memory causes EMPTY\ to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable (OE\) is high. The SN74ALVC7814 is characterized for operation from 0C to 70C.

Market price

型号	描述	库存	价格
SN74ALVC7814-40DLR DISTI # SN74ALVC7814-40DLR-ND	IC MEMORY FIFO 64X18 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ALVC7814-40DLR DISTI # 595-SN74ALVC7814-40D	FIFO 64 x 18 3.3-V ASynch FIFO Memory RoHS: Compliant	0
SN74ALVC7814-40DLR	FIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56 RoHS: Compliant	2250	1000:$5.7800 500:$6.0800 100:$6.3300 25:$6.6000 1:$7.1100

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