CD40102BNSR

CD40102BNSR
Mfr. #:
CD40102BNSR
描述:
Counter ICs CMOS 8-Stage Preset 2-Decd BCD Sync Dwn
生命周期:
制造商新产品。
数据表:
CD40102BNSR 数据表
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更多信息:
CD40102BNSR 更多信息 CD40102BNSR Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
计数器 IC
RoHS:
Y
安装方式:
贴片/贴片
包装/案例:
SO-16
计数器类型:
十年
逻辑系列:
CD4000
位数:
1 bit
计数方法:
同步
计数顺序:
向下
工作电源电压:
3 V to 18 V
最低工作温度:
- 55 C
最高工作温度:
+ 125 C
系列:
CD40102B
打包:
卷轴
功能:
柜台
工作温度范围:
- 55 C to + 125 C
输出电流:
+/- 1.5 mA
品牌:
德州仪器
产品类别:
计数器 IC
出厂包装数量:
2000
子类别:
计数器 IC
单位重量:
0.007079 oz
Tags
CD40102, CD4010, CD401, CD40, CD4
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter 16-SO -55 to 125
***et
Counter Single 8-Bit Sync/Async Decade Down 16-Pin SOP T/R
***ser
Logic - Counters CMOS 8-Stage Preset 2-Decd BCD Sync Dwn
***i-Key
IC SYNC DOWN COUNTER 8STG 16SO
***ark
Counter Logic IC; Counter Type:BCD Down; Clock Speed:4.8MHz; Supply Voltage Range:3V to 18V; Logic Case Style:SOIC; No. of Pins:16; Operating Temperature Range:-55°C to +125°C; Leaded Process Compatible:Yes; Logic Family:CD4000 ;RoHS Compliant: Yes
***AS INSRUMENTS
CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic.
***AS INST
In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period.
***XS
When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102B and 25510 for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.
***as Instruments Inc.
If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long.
***AS INTRUMENTS
This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse.
***OMO Electronic
The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22.
***NS
The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).
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可用性
库存:
Available
订购:
3500
输入数量:
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