AD9572ACPZPEC-RL

Mfr. #:: AD9572ACPZPEC-RL
制造商:: Analog Devices Inc.
描述:: Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output
生命周期:: 制造商新产品。
数据表:: AD9572ACPZPEC-RL 数据表
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产品属性
属性值

制造商：: 模拟设备公司

产品分类：: 时钟驱动器和分配

RoHS：: Y

系列：: AD9572

乘/除因数：: 1:3

输出类型：: LVPECL

最大输出频率：: 156.25 MHz

电源电压 - 最大值：: 3.6 V

最低工作温度：: - 40 C

最高工作温度：: + 85 C

安装方式：: 贴片/贴片

包装/案例：: LFCSP-40

打包：: 卷轴

高度：: 0.73 mm

长度：: 6 mm

输出数量：: 7

类型：: 分配

宽度：: 6 mm

品牌：: 模拟设备公司

最大输入频率：: 25 MHz

湿气敏感：: 是的

产品类别：: 时钟驱动器和分配

出厂包装数量：: 2500

子类别：: 时钟和定时器 IC

Tags: AD9572ACPZP, AD9572, AD957, AD95, AD9

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

AD9572ACPZPEC-RL 描述

***ical: Clock Generator 25MHz-IN 156.25MHz-OUT 40-Pin LFCSP EP T/R

***et Europe: PLL Frequency Synthesizer Dual 40-Pin LFCSP EP T/R

***i-Key: IC PLL CLOCK GEN 25MHZ 40LFCSP

***log Devices: The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates. A second PLL also operates as an integer-N synthesizer and drives two LVPECL or LVDS output buffers for 106.25 MHz operation. No external loop filter components are required, thus conserving valuable design time and board space. The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP) and can be operated from a single 3.3 V supply. The temperature range is -40°C to +85°C. APPLICATIONS Fiber channel line cards, switches, and routers Gigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation

AD9572ACPZPEC-RL 更多信息

Clock & Timing ADI SLP

Market price

型号	制造商	描述	库存	价格
AD9572ACPZPEC-RL DISTI # AD9572ACPZPEC-RLTR-ND	Analog Devices Inc	IC PLL CLOCK GEN 25MHZ 40LFCSP RoHS: Compliant Min Qty: 2500 Container: Tape & Reel (TR)	Temporarily Out of Stock	2500:$6.8864
AD9572ACPZPEC DISTI # 584-AD9572ACPZPEC	Analog Devices Inc	Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output RoHS: Compliant	2	1:$11.3000 10:$10.2500 25:$9.6300 50:$9.2800 100:$8.3400 250:$7.7100 500:$7.2500 1000:$6.5900
AD9572ACPZPEC-R7 DISTI # 584-AD9572ACPZPEC-R7	Analog Devices Inc	Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output RoHS: Compliant	0	750:$6.5900
AD9572ACPZPEC-RL DISTI # 584-AD9572ACPZPEC-R	Analog Devices Inc	Clock Drivers & Distribution Fiber CH/ PLL Core 7 Clock Output RoHS: Compliant	0	2500:$6.5900

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