CD74AC109M96

CD74AC109M96
Mfr. #:
CD74AC109M96
描述:
Flip Flops Dual
生命周期:
制造商新产品。
数据表:
CD74AC109M96 数据表
交货:
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ECAD Model:
更多信息:
CD74AC109M96 更多信息 CD74AC109M96 Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
人字拖
RoHS:
Y
电路数量:
2
逻辑系列:
交流电
逻辑类型:
JK 上升沿触发触发器
极性:
反相/非反相
输入类型:
CMOS、LVTTL
输出类型:
微分
传播延迟时间:
129 ns
高电平输出电流:
- 24 mA
低电平输出电流:
24 mA
电源电压 - 最小值:
1.5 V
电源电压 - 最大值:
5.5 V
最低工作温度:
- 55 C
最高工作温度:
+ 125 C
安装方式:
贴片/贴片
包装/案例:
SOP-16
打包:
卷轴
功能:
双重的
高度:
1.58 mm
长度:
9.9 mm
工作温度范围:
- 55 C to + 125 C
静态电流:
4 uA
系列:
CD74AC109
宽度:
3.91 mm
品牌:
德州仪器
通道数:
2
输入行数:
2
输出线数:
1
工作电源电压:
1.5 V to 5.5 V
产品类别:
人字拖
重置类型:
设置、重置
出厂包装数量:
2500
子类别:
逻辑 IC
单位重量:
0.004998 oz
Tags
CD74AC109M9, CD74AC109M, CD74AC109, CD74AC10, CD74AC1, CD74AC, CD74A, CD74, CD7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and eset 16-SOIC -55 to 125
***ical
Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SOIC T/R
***ark
Ic, Jk-Type Flip Flop, Dual, Soic-16; Logic Family / Base Number:74Ac109; Flip-Flop Type:jk; Propagation Delay:10.3Ns; Frequency:100Mhz; Output Current:24Ma; Logic Case Style:soic; No. Of Pins:16Pins; Trigger Type:positive Edge; Ic Rohs Compliant: Yes
***AS INSTRUM
The ’AC109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
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可用性
库存:
Available
订购:
1986
输入数量:
CD74AC109M96的当前价格仅供参考,如果您想获得最优惠的价格,请提交查询或直接发送电子邮件至我们的销售团队[email protected]
参考价格(美元)
数量
单价
小计金额
1
US$0.60
US$0.60
10
US$0.49
US$4.93
100
US$0.32
US$31.80
1000
US$0.26
US$255.00
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