SN74ALVC7813-40DL

Mfr. #:: SN74ALVC7813-40DL
描述:: IC 64X18 SYNC FIFO MEM 56-SSOP
生命周期:: 制造商新产品。
数据表:: SN74ALVC7813-40DL 数据表
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更多信息:: SN74ALVC7813-40DL 更多信息 SN74ALVC7813-40DL Product Details

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Tags: SN74ALVC7813, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ALVC7813-40DL 评级和评论

B***C

Good. Hope it works as I'm yet to test it.

2019-09-25

E**y

Accurately described, adequately packaged, promptly shipped; 12 days to U.S. delivery.

2019-05-17

SN74ALVC7813-40DL 描述

***et: FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP Tube

***pNet: FIFO Mem Dual Width Uni-Dir 64 x 18 56-Pin SSOP

***i-Key: IC 64X18 SYNC FIFO MEM 56-SSOP

***as Instruments: The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET\) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.

Market price

型号	描述	库存	价格
SN74ALVC7813-40DL DISTI # 296-5171-5-ND	IC 64X18 SYNC FIFO MEM 56-SSOP RoHS: Compliant Min Qty: 80 Container: Tube	Limited Supply - Call
SN74ALVC7813-40DLR DISTI # SN74ALVC7813-40DLR-ND	IC MEMORY FIFO 64X18 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ALVC7813-40DL DISTI # 595-SN74ALVC781340DL	FIFO 16-Bit Buffer/Driver With 3-State Outputs RoHS: Compliant	0
SN74ALVC7813-40DLR DISTI # 595-SN74ALVC7813-40D	FIFO 64 x 18 3.3-V Synch FIFO Memory RoHS: Compliant	0
SN74ALVC7813-40DL	FIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56 RoHS: Compliant	1494	1000:$5.7800 500:$6.0800 100:$6.3300 25:$6.6000 1:$7.1100
SN74ALVC7813-40DLR	FIFO, 64X18, 20ns, Synchronous, CMOS, PDSO56 RoHS: Compliant	1000	1000:$5.7800 500:$6.0800 100:$6.3300 25:$6.6000 1:$7.1100

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