GS8162Z36DB-150I

Mfr. #:: GS8162Z36DB-150I
制造商:: GSI Technology
描述:: SRAM 2.5 or 3.3V 512K x 36 18M
生命周期:: 制造商新产品。
数据表:: GS8162Z36DB-150I 数据表
交货:: DHL FedEx Ups TNT EMS
支付:: T/T Paypal Visa MoneyGram Western Union
ECAD Model:
更多信息:: GS8162Z36DB-150I 更多信息

产品属性
属性值

制造商：: GSI技术

产品分类：: 静态随机存取存储器

打包：: 托盘

系列：: GS8162Z36DB

品牌：: GSI技术

湿气敏感：: 是的

产品类别：: 静态随机存取存储器

出厂包装数量：: 21

子类别：: 内存和数据存储

商品名：: 静态随机存取存储器

Tags: GS8162Z36DB-1, GS8162Z36DB, GS8162Z36D, GS8162Z3, GS8162Z, GS8162, GS816, GS81, GS8

Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

GS8162Z36DB-150I 评级和评论

M***v

The goods received, but the delivery is very long (more than 3 months). I have not checked yet, but i think that everything is fine, 9014-very common transistors, this is not the last iphone. However, the product although it was a long time, but its price is very attractive. I bet five for that.

2019-09-03

E**d

704190161392971. order

2019-05-29

M***i

OK as described

2019-05-24

G***v

Shipping 45 days to mordovia, track was not tracked. Outwardly satisfactory quality, the resistance of the drain of the source corresponds to the declared characteristics, within 0,5 ohms. In the work has not yet checked, well, i think. That the quality corresponds to the declared.

2019-07-10

GS8162Z36DB-150I 描述

***et: SRAM Chip Sync Quad 2.5V/3.3V 18M-Bit 512K x 36 7.5ns/3.8ns 119-Pin F-BGA

GS8162Z36DB-150I 更多信息

NBT SRAMs: GSI Technology NBT SRAMs are 144Mbit and 288Mbit Synchronous Static SRAMs that allow utilization of all available bus bandwidth. The SRAMs achieve this by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. The devices' simplified interface is designed to use a data bus's maximum bandwidth. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock.

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