CLVTH16543MDLREP

CLVTH16543MDLREP
Mfr. #:
CLVTH16543MDLREP
描述:
Bus Transceivers Mil Enhance 3.3V ABT 16B Registered Xcvr
生命周期:
制造商新产品。
数据表:
CLVTH16543MDLREP 数据表
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CLVTH16543MDLREP 更多信息 CLVTH16543MDLREP Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
总线收发器
RoHS:
Y
逻辑系列:
LVT
输入电平:
LVTTL
输出电平:
LVTTL
输出类型:
3-State
高电平输出电流:
- 32 mA
低电平输出电流:
64 mA
传播延迟时间:
6.5 ns
电源电压 - 最大值:
3.6 V
电源电压 - 最小值:
2.7 V
最低工作温度:
- 55 C
最高工作温度:
+ 125 C
包装/案例:
SSOP-56
打包:
卷轴
功能:
锁存收发器
高度:
2.59 mm
长度:
18.41 mm
电路数量:
2
工作温度范围:
- 55 C to + 125 C
产品:
双CMOS
系列:
SN74LVTH16543-EP
技术:
双CMOS
宽度:
7.49 mm
品牌:
德州仪器
安装方式:
贴片/贴片
通道数:
16
电源电流 - 最大值:
5 mA
工作电源电压:
3.3 V
极性:
同相
产品类别:
总线收发器
出厂包装数量:
1000
子类别:
逻辑 IC
第 # 部分别名:
V62/04715-02YE
单位重量:
0.024508 oz
Tags
CLVTH165, CLVTH1, CLVTH, CLVT, CLV
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
Enhanced Product 3.3-V Abt 16-Bit Registered Transceiver With 3-State Outputs 56-SSOP -55 to 125
***et
Bus XCVR Dual 16-CH 3-ST 56-Pin SSOP T/R
***i-Key
IC TXRX NON-INVERT 3.6V 56SSOP
***ark
Transceiver Logic IC; Logic Family:LVT; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Package/Case:56-SSOP; No. of Pins:56; Operating Temperature Range:-55°C to +125°C; Leaded Process Compatible:Yes; No. of Bits:16 ;RoHS Compliant: Yes
***as Instruments (TI)
The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCC operation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEAB or LEBA) and output–enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
***AS INSRUMENT
The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A–to–B latches are transparent; a subsequent low–to–high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs.
***AS USD
Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
***AS INS
When VCC is between 0 and 1.5 V, the device is in the high–impedance state during power up or power down. However, to ensure the high–impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current–sinking capability of the driver.
***AS INSTRUM
This device is fully specified for hot–insertion applications using Ioff and power–up 3–state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power–up 3–state circuitry places the outputs in the high–impedance state during power up and power down, which prevents driver conflict.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
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可用性
库存:
Available
订购:
3500
输入数量:
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