74ALVCH162268DLRG4

74ALVCH162268DLRG4
Mfr. #:
74ALVCH162268DLRG4
描述:
Universal Bus Functions Triple Buffer/Driver W/Open-Drain Output
生命周期:
制造商新产品。
数据表:
74ALVCH162268DLRG4 数据表
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更多信息:
74ALVCH162268DLRG4 更多信息 74ALVCH162268DLRG4 Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
通用总线功能
RoHS:
Y
逻辑类型:
注册巴士交换器
逻辑系列:
74AL
电路数量:
1
传播延迟时间:
5.9 ns, 5.4 ns
电源电压 - 最大值:
3.6 V
电源电压 - 最小值:
1.65 V
最低工作温度:
- 40 C
最高工作温度:
+ 85 C
包装/案例:
SSOP-56
打包:
卷轴
功能:
注册巴士交换器
高度:
2.59 mm
长度:
18.41 mm
组织:
12 x 2:1
输出类型:
3-State
供应类型:
单身的
宽度:
7.49 mm
品牌:
德州仪器
安装方式:
贴片/贴片
输入行数:
12
输出线数:
24
高电平输出电流:
- 24 mA
低电平输出电流:
24 mA
最大时钟频率:
0.15 GHz, 0.125 GHz, 0.12 GHz
工作电源电压:
1.8 V, 2.5 V, 3.3 V
极性:
同相
产品类别:
通用总线功能
出厂包装数量:
1
子类别:
逻辑 IC
单位重量:
0.024508 oz
Tags
74ALVCH162268, 74ALVCH16226, 74ALVCH1622, 74ALVCH162, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56
***ark
Universal Bus Function IC; Logic Family:ALVC; Supply Voltage Min:1.65V; Supply Voltage Max:3.6V; Package/Case:56-SSOP; No. of Pins:56; Operating Temperature Range:-40°C to +85°C; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN)\ inputs are low. The select (SEL)\ line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). These control terminals are registered, so bus direction changes are synchronous with CLK. The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
型号 描述 库存 价格
74ALVCH162268DLRG4
DISTI # 74ALVCH162268DLRG4-ND
IC RGSTRD BUS EXCHANGER 56SSOP
RoHS: Not compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    74ALVCH162268DLRG4
    DISTI # 595-74ALVCH162268DG4
    Universal Bus Functions Triple Buffer/Driver W/Open-Drain Output
    RoHS: Compliant
    0
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      可用性
      库存:
      Available
      订购:
      2000
      输入数量:
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