TMS320C6457CCMH2

TMS320C6457CCMH2
Mfr. #:
TMS320C6457CCMH2
描述:
Digital Signal Processors & Controllers - DSP, DSC Fixed-Pt Dig Signal Proc
生命周期:
制造商新产品。
数据表:
TMS320C6457CCMH2 数据表
交货:
DHL FedEx Ups TNT EMS
支付:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
更多信息:
TMS320C6457CCMH2 更多信息 TMS320C6457CCMH2 Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
数字信号处理器和控制器 - DSP、DSC
RoHS:
Y
安装方式:
贴片/贴片
包装/案例:
FCBGA-688
系列:
TMS320C6457
产品:
DSP
核:
C64x
最大时钟频率:
1.2 GHz
程序内存大小:
2 MB
数据内存大小:
32 kB
工作电源电压:
3.3 V
最低工作温度:
0 C
最高工作温度:
+ 100 C
打包:
托盘
高度:
3.3 mm
长度:
23 mm
程序存储器类型:
高速缓存、ROM、SRAM
宽度:
23 mm
品牌:
德州仪器
数据ROM大小:
64 kB
接口类型:
HPI, I2C
数据总线宽度:
16 bit
教学类型:
固定点
MMACS:
9600 MMACs
湿气敏感:
是的
定时器/计数器的数量:
2 Timer
产品类别:
DSP - 数字信号处理器和控制器
出厂包装数量:
60
子类别:
嵌入式处理器和控制器
电源电压 - 最大值:
3.465 V
电源电压 - 最小值:
1.067 V
Tags
TMS320C6457CC, TMS320C6457, TMS320C645, TMS320C64, TMS320C6, TMS320C, TMS320, TMS32, TMS3, TMS
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***as Instruments
Communications Infrastructure Digital Signal Processor 688-FCBGA 0 to 95
***ical
DSP Fixed-Point 32bit 1.2GHz 9600MIPS 688-Pin FCBGA Tray
***p One Stop Global
DSP Fixed-Point 32-Bit 1.2GHz 9600MIPS 688-Pin FCBGA
***ponent Sense
IC DSP TMS320C6457CCMH2 BGA688 1.2GHz FI
*** Source Electronics
Communications Infrastructure Digital Signal Processor
***i-Key
IC DSP FIXED-POINT 688FCBGA
***ark
320C6457 1.2GHZ
***AS USD
The TMS320C64x+™ DSPs (including the TMS320C6457 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6457 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.
***
Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6457 device offers cost-effective solutions to high-performance DSP programming challenges. The C6457 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
***NS
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.
***AS INSTRUMENT
The C6457 device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.
***AS INSTRUMENTS INC
The C6457 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6457 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.
***
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6457 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.
***AS
The C6457 device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor (VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out through the EDMA3 controller.
***AS INST
The C6457 device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.
Processors
OMO Electronic Processors provide a comprehensive portfolio, proven software, and worldwide support enabling industry-leading automotive and industrial solutions. TI is dedicated to advancing and optimizing today’s processors to meet tomorrow’s intelligence, performance and cost requirements in automotive and industrial applications. Scalable hardware and software platforms with common code allow designers to seamlessly reuse and migrate across devices to protect future investment.
型号 描述 库存 价格
TMS320C6457CCMH2
DISTI # 296-43489-ND
IC DSP FIXED-POINT 688FCBGA
RoHS: Compliant
Min Qty: 1
Container: Tray
36In Stock
  • 60:$115.1252
  • 10:$117.6280
  • 1:$123.4700
TMS320C6457CCMH2
DISTI # TMS320C6457CCMH2
DSP Fixed-Point 32-Bit 1.2GHz 9600MIPS 688-Pin FCBGA (Alt: TMS320C6457CCMH2)
RoHS: Compliant
Min Qty: 1
Europe - 20
  • 1:€119.1900
  • 10:€115.6900
  • 25:€112.1900
  • 50:€109.1900
  • 100:€106.0900
  • 500:€103.1900
  • 1000:€100.5900
TMS320C6457CCMH2
DISTI # TMS320C6457CCMH2
DSP Fixed-Point 32-Bit 1.2GHz 9600MIPS 688-Pin FCBGA (Alt: TMS320C6457CCMH2)
RoHS: Compliant
Min Qty: 60
Asia - 0
    TMS320C6457CCMH2
    DISTI # TMS320C6457CCMH2
    DSP Fixed-Point 32-Bit 1.2GHz 9600MIPS 688-Pin FCBGA - Trays (Alt: TMS320C6457CCMH2)
    RoHS: Compliant
    Min Qty: 60
    Container: Tray
    Americas - 0
    • 60:$139.1900
    • 120:$135.7900
    • 240:$130.4900
    • 360:$127.2900
    • 600:$124.9900
    TMS320C6457CCMH2Communications Infrastructure Digital Signal Processor60
    • 1000:$94.8000
    • 750:$95.1000
    • 500:$101.7800
    • 250:$104.2800
    • 100:$107.6200
    • 25:$110.9500
    • 10:$114.2900
    • 1:$120.9700
    TMS320C6457CCMH2
    DISTI # 595-TMS320C6457CCMH2
    Digital Signal Processors & Controllers - DSP, DSC Fixed-Pt Dig Signal Proc
    RoHS: Compliant
    0
    • 60:$115.1400
    图片 型号 描述
    TMDSEMU560V2STM-UE

    Mfr.#: TMDSEMU560V2STM-UE

    OMO.#: OMO-TMDSEMU560V2STM-UE

    Emulators / Simulators XDS560 Class High Speed Emulators
    TMDSEMU200-U

    Mfr.#: TMDSEMU200-U

    OMO.#: OMO-TMDSEMU200-U-TEXAS-INSTRUMENTS

    XDS200 USB JTAG EMULATOR
    TMDSEMU560V2STM-U

    Mfr.#: TMDSEMU560V2STM-U

    OMO.#: OMO-TMDSEMU560V2STM-U-TEXAS-INSTRUMENTS

    EMULATOR TRACE SYSTEM USB
    TMDSEMU560V2STM-UE

    Mfr.#: TMDSEMU560V2STM-UE

    OMO.#: OMO-TMDSEMU560V2STM-UE-TEXAS-INSTRUMENTS

    EMULATOR TRACE SYSTEM XDS560
    可用性
    库存:
    Available
    订购:
    2500
    输入数量:
    TMS320C6457CCMH2的当前价格仅供参考,如果您想获得最优惠的价格,请提交查询或直接发送电子邮件至我们的销售团队[email protected]
    参考价格(美元)
    数量
    单价
    小计金额
    60
    US$115.14
    US$6 908.40
    由于2021年半导体供不应求,低于2021年之前的正常价格,请发询价确认。
    从...开始
    最新产品
    Top