SN74ACT3641-30PQ

Mfr. #:: SN74ACT3641-30PQ
描述:: IC CLOCKED FIFO MEMORY 132-QFP
生命周期:: 制造商新产品。
数据表:: SN74ACT3641-30PQ 数据表
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更多信息:: SN74ACT3641-30PQ 更多信息 SN74ACT3641-30PQ Product Details

产品属性
属性值

制造商: 德州仪器

产品分类: 逻辑 - FIFO 存储器

系列: 74ACT

打包: 托盘

包装盒: 132-BQFP Bumpered

工作温度: 0°C ~ 70°C

安装型: 表面贴装

功能: 同步

电压供应: 4.5 V ~ 5.5 V

供应商-设备-包: 132-BQFP (24.54x24.54)

内存大小: 36K (1K x 36)

数据速率: 33.4MHz

访问时间: 15ns

最大电流供应: 400μA

巴士定向: 双向

扩展型: 深度、宽度

可编程标志支持: 是的

转发能力: 是的

FWFT-支持: 不

Tags: SN74ACT364, SN74ACT36, SN74ACT3, SN74ACT, SN74AC, SN74A, SN74, SN7

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ACT3641-30PQ 评级和评论

A***V

Everything came quickly enough and what i ordered

2019-05-11

H***J

item as per specs, supplier good

2019-09-09

S***s

2019-06-12

V***v

Thank you!

2019-05-20

SN74ACT3641-30PQ 描述

***et: FIFO Mem Sync Dual Depth Bi-Dir 1K x 36 132-Pin BQFP Tray

***i-Key: IC CLOCKED FIFO MEMORY 132-QFP

***as Instruments: The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 12 ns. The 1024 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices are used in parallel to create wider datapaths. Expansion is also possible in word depth. The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the AF\ and AE\ flags of the FIFO can be programmed from port A or through a serial input. The SN74ACT3641 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)

Market price

型号	描述	库存	价格
SN74ACT3641-30PQ DISTI # 296-4413-ND	IC CLOCKED FIFO MEMORY 132-QFP RoHS: Compliant Min Qty: 36 Container: Tray	Limited Supply - Call
SN74ACT3641-30PQ DISTI # 595-SN74ACT3641-30PQ	FIFO 1024 x 36 synch FIFO Memory RoHS: Compliant	0
SN74ACT3641-30PQ	Bi-Directional FIFO, 1KX36, 15ns, Synchronous, CMOS, PQFP132 RoHS: Compliant	278	1000:$25.4100 500:$26.7500 100:$27.8400 25:$29.0400 1:$31.2700

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