SN74LVC823ANSR

SN74LVC823ANSR
Mfr. #:
SN74LVC823ANSR
描述:
Flip Flops 9-Bit Bus Intfc FlipFlop W/3-St Otpt
生命周期:
制造商新产品。
数据表:
SN74LVC823ANSR 数据表
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ECAD Model:
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SN74LVC823ANSR 更多信息 SN74LVC823ANSR Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
人字拖
RoHS:
Y
电路数量:
1
逻辑系列:
74LV
逻辑类型:
总线接口触发器
极性:
同相
输入类型:
单端
输出类型:
单端
传播延迟时间:
8.9 ns
高电平输出电流:
- 24 mA
低电平输出电流:
24 mA
电源电压 - 最小值:
1.65 V
电源电压 - 最大值:
3.6 V
最低工作温度:
- 40 C
最高工作温度:
+ 85 C
安装方式:
贴片/贴片
包装/案例:
SO-24
打包:
卷轴
功能:
D型总线接口
高度:
1.95 mm
长度:
15 mm
静态电流:
10 uA
宽度:
5.3 mm
品牌:
德州仪器
通道数:
9
输入行数:
9
输出线数:
3
工作电源电压:
1.65 V to 3.6 V
产品类别:
人字拖
重置类型:
主复位
出厂包装数量:
1
子类别:
逻辑 IC
单位重量:
0.010857 oz
Tags
SN74LVC823, SN74LVC82, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
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We guarantee 100% customer satisfaction.

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We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE POS TRG SNGL 24SO
***el Nordic
Contact for details
***as Instruments
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock. A buffered output-enable (OE)\ input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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可用性
库存:
Available
订购:
3500
输入数量:
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