SN74ALS163BDBRG4

Mfr. #:: SN74ALS163BDBRG4
描述:: Counter ICs Synch 4B Binary Counters
生命周期:: 制造商新产品。
数据表:: SN74ALS163BDBRG4 数据表
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更多信息:: SN74ALS163BDBRG4 更多信息 SN74ALS163BDBRG4 Product Details

产品属性
属性值

制造商：: 德州仪器

产品分类：: 计数器 IC

RoHS：: Y

安装方式：: 贴片/贴片

包装/案例：: SSOP-16

计数器类型：: 二进制

逻辑系列：: TTL

位数：: 4

计数方法：: 同步

工作电源电压：: 4.5 V to 5.5 V

打包：: 卷轴

品牌：: 德州仪器

产品类别：: 计数器 IC

出厂包装数量：: 1

子类别：: 计数器 IC

单位重量：: 0.004536 oz

Tags: SN74ALS163BDB, SN74ALS163BD, SN74ALS163, SN74ALS16, SN74ALS1, SN74ALS, SN74AL, SN74A, SN74, SN7

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SN74ALS163BDBRG4 描述

***i-Key: IC COUNTER BINARY 4BIT 16SSOP

***ser: Logic - Counters Synch 4B Binary Counters

***ark: Counter Logic IC; Logic Family:ALS; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:16-SSOP; No. of Pins:16; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes; Output Type:TTL ;RoHS Compliant: Yes

***as Instruments: These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The ï¿½ALS161B, ï¿½ALS163B, ï¿½AS161, and ï¿½AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ï¿½ALS161B and ï¿½AS161 devices is asynchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD\, or enable inputs. The clear function for the SN54ALS162B, ï¿½ALS163B, and ï¿½AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with QA high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of ï¿½55C to 125C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0C to 70C.

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SN74ALS163BDBRG4

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes