SN74ALVC7813-25DLR

Mfr. #:: SN74ALVC7813-25DLR
描述:: FIFO 64 x 18 3.3-V Synch FIFO Memory
生命周期:: 制造商新产品。
数据表:: SN74ALVC7813-25DLR 数据表
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更多信息:: SN74ALVC7813-25DLR 更多信息 SN74ALVC7813-25DLR Product Details

产品属性
属性值

制造商: 德州仪器

产品分类: 逻辑 - FIFO 存储器

系列: 74ALVC

打包: 卷带 (TR)

包装盒: 56-BSSOP (0.295", 7.50mm Width)

工作温度: 0°C ~ 70°C

安装型: 表面贴装

功能: 同步

电压供应: 3 V ~ 3.6 V

供应商-设备-包: 56-SSOP

内存大小: 1.125K (64 x 18)

数据速率: 40MHz

访问时间: 15ns

最大电流供应: 40μA

巴士定向: 单向

扩展型: 宽度

可编程标志支持: 是的

转发能力: 不

FWFT-支持: 不

Tags: SN74ALVC7813-2, SN74ALVC7813, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7

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We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74ALVC7813-25DLR 描述

***et: FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R

***i-Key: IC MEMORY FIFO 64X18 56-SSOP

***as Instruments: The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET\) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.

Market price

型号	描述	库存	价格
SN74ALVC7813-25DLR DISTI # SN74ALVC7813-25DLR-ND	IC MEMORY FIFO 64X18 56-SSOP RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Limited Supply - Call
SN74ALVC7813-25DLR	FIFO, 64X18, 15ns, Synchronous, CMOS, PDSO56 RoHS: Compliant	9000	1000:$3.1800 500:$3.3500 100:$3.4900 25:$3.6400 1:$3.9200

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