SN74ABT853DBRE4

SN74ABT853DBRE4
Mfr. #:
SN74ABT853DBRE4
描述:
Bus Transceivers 8 to 9-Bit Parity Bus Transceivers
生命周期:
制造商新产品。
数据表:
SN74ABT853DBRE4 数据表
交货:
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支付:
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ECAD Model:
更多信息:
SN74ABT853DBRE4 更多信息 SN74ABT853DBRE4 Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
总线收发器
RoHS:
Y
逻辑系列:
74ABT
输入电平:
TTL
输出电平:
TTL
输出类型:
3-State
高电平输出电流:
- 32 mA
低电平输出电流:
64 mA
传播延迟时间:
4.8 ns
电源电压 - 最大值:
5.5 V
电源电压 - 最小值:
4.5 V
最低工作温度:
- 40 C
最高工作温度:
+ 85 C
包装/案例:
SSOP-24
打包:
卷轴
功能:
带有奇偶校验器的总线收发器
高度:
1.95 mm
长度:
8.2 mm
电路数量:
1
产品:
双CMOS
静态电流:
24 mA
技术:
双CMOS
宽度:
5.3 mm
品牌:
德州仪器
安装方式:
贴片/贴片
通道数:
8
电源电流 - 最大值:
38 mA
工作电源电压:
4.5 V to 5.5 V
极性:
同相
产品类别:
总线收发器
出厂包装数量:
1
子类别:
逻辑 IC
单位重量:
0.059966 oz
Tags
SN74ABT853DB, SN74ABT853D, SN74ABT853, SN74ABT85, SN74ABT8, SN74AB, SN74A, SN74, SN7
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We guarantee 100% customer satisfaction.

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INVERT 24SSOP
***as Instruments
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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FIFO 512 x 18 x 2 bidir ASynch FIFO Memory
可用性
库存:
Available
订购:
5000
输入数量:
SN74ABT853DBRE4的当前价格仅供参考,如果您想获得最优惠的价格,请提交查询或直接发送电子邮件至我们的销售团队[email protected]
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