SN74LV374ADGVR

SN74LV374ADGVR
Mfr. #:
SN74LV374ADGVR
描述:
Flip Flops Octal Edge-Trig D-Ty F-F W/3-State Otpt
生命周期:
制造商新产品。
数据表:
SN74LV374ADGVR 数据表
交货:
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支付:
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ECAD Model:
更多信息:
SN74LV374ADGVR 更多信息 SN74LV374ADGVR Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
人字拖
RoHS:
Y
电路数量:
8
逻辑系列:
74LV
逻辑类型:
D 型触发器
极性:
同相
输入类型:
单端
输出类型:
单端
传播延迟时间:
19.3 ns
高电平输出电流:
- 16 mA
低电平输出电流:
16 mA
电源电压 - 最小值:
2 V
电源电压 - 最大值:
5.5 V
最低工作温度:
- 40 C
最高工作温度:
+ 85 C
安装方式:
贴片/贴片
包装/案例:
TVSOP-20
打包:
卷轴
功能:
D型总线接口
高度:
1.05 mm
长度:
5 mm
静态电流:
20 uA
宽度:
4.4 mm
品牌:
德州仪器
通道数:
8
输入行数:
2
输出线数:
1
工作电源电压:
2 V to 5.5 V
产品类别:
人字拖
出厂包装数量:
1
子类别:
逻辑 IC
单位重量:
0.002123 oz
Tags
SN74LV374AD, SN74LV374A, SN74LV374, SN74LV37, SN74LV3, SN74LV, SN74L, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20TVSOP
***ark
Flip-Flop Logic IC; Flip Flop Type:D; Trigger Type:Positive Edge; Output Type:Tri-State Non-Inverted; Supply Voltage Range:2V to 5.5V; Logic Case Style:TVSOP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C ;RoHS Compliant: Yes
***as Instruments
The ’LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
图片 型号 描述
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全新原装
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Mfr.#: SN74LV393ADRG4

OMO.#: OMO-SN74LV393ADRG4-1190

Counter ICs Dual 4B Binary Counters
可用性
库存:
Available
订购:
4500
输入数量:
SN74LV374ADGVR的当前价格仅供参考,如果您想获得最优惠的价格,请提交查询或直接发送电子邮件至我们的销售团队[email protected]
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