SN74ACT3641-30PQ

SN74ACT3641-30PQ
Mfr. #:
SN74ACT3641-30PQ
描述:
FIFO 1024 x 36 synch FIFO Memory
生命周期:
制造商新产品。
数据表:
SN74ACT3641-30PQ 数据表
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SN74ACT3641-30PQ 更多信息 SN74ACT3641-30PQ Product Details
产品属性
属性值
制造商:
德州仪器
产品分类:
先进先出
RoHS:
Y
数据总线宽度:
36 bit
巴士方向:
双向
内存大小:
36 kbit
计时类型:
同步
组织:
1 k x 36
电路数量:
2
最大时钟频率:
33.4 MHz
访问时间:
15 ns
电源电压 - 最大值:
5.5 V
电源电压 - 最小值:
4.5 V
电源电流 - 最大值:
0.4 mA
最低工作温度:
0 C
最高工作温度:
+ 70 C
包装/案例:
BQFP-132
打包:
管子
高度:
3.56 mm
宽度:
24.13 mm
品牌:
德州仪器
安装方式:
贴片/贴片
湿气敏感:
是的
工作电源电压:
5 V
产品类别:
先进先出
出厂包装数量:
1
子类别:
内存和数据存储
单位重量:
0.162567 oz
Tags
SN74ACT364, SN74ACT36, SN74ACT3, SN74ACT, SN74AC, SN74A, SN74, SN7
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We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Depth Bi-Dir 1K x 36 132-Pin BQFP Tray
***i-Key
IC CLOCKED FIFO MEMORY 132-QFP
***as Instruments
The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 12 ns. The 1024 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices are used in parallel to create wider datapaths. Expansion is also possible in word depth. The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF\) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE\) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the AF\ and AE\ flags of the FIFO can be programmed from port A or through a serial input. The SN74ACT3641 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004)
型号 描述 库存 价格
SN74ACT3641-30PQ
DISTI # 296-4413-ND
IC CLOCKED FIFO MEMORY 132-QFP
RoHS: Compliant
Min Qty: 36
Container: Tray
Limited Supply - Call
    SN74ACT3641-30PQ
    DISTI # 595-SN74ACT3641-30PQ
    FIFO 1024 x 36 synch FIFO Memory
    RoHS: Compliant
    0
      SN74ACT3641-30PQBi-Directional FIFO, 1KX36, 15ns, Synchronous, CMOS, PQFP132
      RoHS: Compliant
      278
      • 1000:$25.4100
      • 500:$26.7500
      • 100:$27.8400
      • 25:$29.0400
      • 1:$31.2700
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      FIFO 512 x 36 synchronous FIFO memory
      可用性
      库存:
      Available
      订购:
      1000
      输入数量:
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