CD4029BPWG4

Mfr. #:: CD4029BPWG4
描述:: IC PRESET UP/DWN COUNTER 16TSSOP
生命周期:: 制造商新产品。
数据表:: CD4029BPWG4 数据表
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更多信息:: CD4029BPWG4 更多信息 CD4029BPWG4 Product Details

产品属性
属性值

制造商: 德州仪器

产品分类: 逻辑 - 计数器、分频器

系列: 4000B

打包: 管替代包装

包装盒: 16-TSSOP (0.173", 4.40mm Width)

工作温度: -55°C ~ 125°C

安装型: 表面贴装

方向: 向上，向下

电压供应: 3 V ~ 18 V

供应商-设备-包: 16-TSSOP

元素数: 1

逻辑型: 二进制计数器，十年

每个元素的位数: 4

重启: 异步

定时: 同步

计数率: 11MHz

触发类型: 上升沿

Tags: CD4029BP, CD4029B, CD4029, CD402, CD40, CD4

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Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

CD4029BPWG4 描述

***ser: Counter ICs CMOS Presettable Up/Down Counter

***ark: Counter Logic IC; Logic Family:CD4000; Supply Voltage Min:3V; Supply Voltage Max:18V; Package/Case:16-TSSOP; No. of Pins:16; Operating Temperature Range:-55°C to +125°C; Input Type:CMOS; Leaded Process Compatible:Yes ;RoHS Compliant: Yes

***as Instruments: CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low. The CARRY-IN\ signal in the low state can thus be considered a CLOCK ENABLE\. The CARRY-IN\ terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD4029B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Market price

型号	描述	库存	价格
CD4029BPWG4 DISTI # CD4029BPWG4-ND	IC PRESET UP/DWN COUNTER 16TSSOP RoHS: Compliant Min Qty: 2160 Container: Tube	Limited Supply - Call

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